The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Radio frequency (RF) communications channels are established by wireless communications devices in a wireless network. Receiving devices for high speed data communications channels typically include a phase-locked loop (PLL) circuit that locks onto the phase of a received data stream.
Referring now to FIG. 1, an exemplary PLL 10 includes a phase detector (PD) 12, a charge-pump 14, a loop filter 16, a voltage controlled oscillator (VCO) 18, and a frequency divider 20. The VCO 18 generates an output signal that is divided by the frequency divider 20 and fed back to the PD 12. The PD 12 detects a phase difference between a reference frequency signal 22 (such as the received data stream) and the feedback or divided output signal 24. The PD 12 generally generates UP and DOWN phase difference signals 30, 32. UP signals indicate positive differences between the reference signal and the output signal and DOWN signals represent negative differences.
The charge-pump 14 receives the phase difference signals 30, 32 and generates an output signal that is used to adjust the output of the VCO 18. Performance of the charge-pump 14 is typically characterized by switching speed and phase offset. Phase offset refers to the voltage generated by the charge-pump 14 when the phase of the reference signal 22 and the feedback signal 24 are the same. The phase offset of the charge-pump 14 may be zero.
The output 34 of the charge-pump 14 is filtered by the loop filter 16. The loop filter 16 may include a capacitance-based integrating circuit, although other types of filters may be used. The desired frequency for the output signal 28 of the VCO 18 may be different than the frequency of the reference signal 22. The frequency divider 20 adjusts the frequency of the output signal 28 based on the ratio of the desired output frequency to the reference frequency.